IRS233(0,2)(D)(S&J)PbF
HIN1,2,3
A
B
LIN1, 2, 3
ITRIP
FAULT
HO1, 2, 3
LO1, 2, 3
Figure 4: Input/output timing diagram
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a
minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power
switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is
automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified
by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals.
The deadtime circuitry of the IRS233(0,2)(D) is matched with respect to the high- and low-side outputs of a given channel;
additionally, the deadtimes of each of the three channels are matched.
Figure 5: Illustration of deadtime
www.irf.com
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